Field Effect Transistor technology is a relatively highly developed art, which is currently under extensive development and investigation by the art in general. There are a sizeable number of published articles, patents and text books directed to theory, structure, methods of fabrication, process technology, circuitry and application of field effect devices.
MOSFETs (Metal-Oxide Silicon Field Effect Transistors), MISFETs (Metal Insulator Silicon Field Effect Transistors) and IGFETs (Insulated Gate Field Effect Transistors) are terms extensively employed in the art and possessing well established definitions in the art. "N-channel", "P-channel", "Enhancement Mode", "Depletion Mode" and "CMOS" (Complementary Metal Oxide Silicon) are additional terms extensively employed in the art and possessing well established definitions. At least certain of the foregoing terms will be used hereinafter. When used hereinafter, their use will be in full accord with the generally established definition given said phrase or word in the art.
Numerous texts fully explain the theory of operation of field effect transistors. Two such texts are: (1) "MOSFET in Circuit Design" by Robert H. Crawford (Texas Instrument Series) McGraw Hill, copyright 1967 by Texas Instruments Incorporated and (2) "ELECTRONICS: BJTs, FETs and Microcircuits" by E. James Angelo, Jr., McGraw Hill Electrical and Electronic Engineering Series, copyrighted 1969 by McGraw Hill.
A publication tracing the development of the field effect transistor, evidencing its high state of development, and explaining in non-mathematical terms its operation is the following article: "Metal-Oxide Semiconductor Technology" by William C. Hittinger, Scientific Americana, August 1973, pages 48 through 57.
U.S. Pat. No. 3,641,511 granted Feb. 8, 1972 to James R. Cricchi et al is directed to a "Complementary MOSFET Integrated Circuit Memory". A random access nondestructive voltage readout complementary MOSFET memory fabricated on a single integrated circuit "chip" including not only a plurality of identical memory cells arranged in a maxtrix array, but also the digital address decoding logic circuitry as well as the input/out buffer circuitry including data line driver circuits insulating the memory cell array from external data lines and input/output control logic circuits insulating the address decoding logic circuitry and the data line driver circuits from external read/write control and strobe input sources. Both N-channel and P-channel MOSFETs are fabricated adjacent to one another as complementary pairs on the same "chip" with the exclusion of at least one guard ring diffusion region between adjacent drain diffusion regions of the complementary pairs by the inclusion of a relatively thick oxide layer (15-20KA) which operates to minimize internal interconnection line capacitance and parasitic surface channels. The data line drivers are bidirectional to provide nondestructive readout, fast readout response, noise immunity and low-input capacitance. Each memory cell is comprised of two pairs of complementary MOSFETs coupled together as cross-coupled inverter circuits. Additionally, each cell is provided with a pair of parallel connected complementary MOSFETs acting as an input/output transmission switch and are coupled to a common input/output internal data line and operated by separate address command signals from the address decoding logic circuit. Another pair of parallel connected complementary MOSFETs are coupled to the memory cell as a feedback transmission switch and are operated by still other separate address command signals from the address decoding logic circuit. The address command logic utilized to operate the parallel connected pairs comprising the input/output transmission switch and the feedback transmission switch is timed to permit nondestructive readout of the memory cell.
U.S. Pat. No. 3,718,915 granted Feb. 27, 1973 to William R. Lattin is directed to "Opposite Conductivity Gating Circuit for Refreshing Information in Semiconductor Memory Cells". Circuit for refreshing information provided as different potentials in semiconductor cells of a dynamic metal oxide semiconductor (MOS) random access memory array with greater speed and less critical clock pulse timing. The circuit is also used for reading information from cells. The circuit may be used in a memory with a plurality of cells provided on semiconductor chip, as for example, 1,024 cells arranged in 32 rows and 32 columns, each providing one information bit. The memory may be of the dual rail type or the single rail type and is illustrated as a dual rail memory with a DATA bus which applies potentials to the cells in each column and a READ bus for indicating the information in the cells. The cells may include silicon gate field effect transistors (FET) which are all of the same conductivity type, with the circuit for refreshing the information being formed by devices of complimentary types. A first pair of complimentary MOSFET's form a pair of gates selectively rendered operative by the READ bus for applying one of the two potentials which form the information bits in the cells to an interim storage point. A transmission gate applies the stored potential to the DATA bus to refresh the information potential in the cell. A single circuit restores the potentials of all the cells in a column at high speed, with low voltage operation and non-critical timing of clock pulses.
Reference is made to U.S. Pat. No. 3,740,732 granted June 19, 1973 to Pierre M. Frandon and directed to a "Dynamic Data Storage Cell". The dynamic data storage cell disclosed in U.S. Pat. No. 3,740,732 requires only one insulated field effect transistor to store binary data. The drain of the FET is connected to a data input line and data is stored at the source node of the transistor by inherent capacitance between the source diffusion and the substrate. The capacitance of the source electrode is enhanced by forming a heavily doped layer to underlie a portion of the source diffusion. Using the substrate as circuit ground enables the fabrication of an array of transistors for a random access memory wherein the surface area of the semiconductor chip is minimized.
U.S. Pat. No. 3,757,310 granted Sept. 4, 1973 to Brian F. Croxon is directed to a "Memory Address Selection Apparatus Including Isolation Circuits". A semiconductor memory chip includes buffer circuits positioned between the input address lines applied to the chip and the decoder circuits coupled to the cells of the memory array. Each of the buffer circuits is arranged to translate low level logic address signals applied to its input terminal into a pair of high level complementary signals suitable for driving a pair of address selection lines applied to the input terminals of the decoder circuits. During a first interval of a memory cycle prior to address selection time each buffer circuit is forced to a predetermined state. This forces each pair of address selection lines to a first state selected to enable each of the decoder circuits to be precharged to a first predetermined state during the first interval. Subsequently, during address selection time, a clocking signal conditions each of the buffer circuits to switch only one address selection line of each pair of lines from a first state to a second state in accordance with the state of the low level address information signal applied to its input terminal. This causes each of the decoder circuits which has one of its input terminals forced to a second state to discharge rapidly from the first predetermined state with only the addressed decoder circuits remaining at the first predetermined state.
U.S. Pat. No. 3,796,893 granted Mar. 12, 1974 to Charles R. Hoffman et al is directed to "Peripheral Circuitry for Dynamic MOS RAMS". Improved circuits for a dynamic MOS RAM having a storage array of inverting storage cells, including an improved buffer, an improved write circuit and a sense circuit. The input buffer circuit includes a dynamic latch circuit clocked by the first clock complement signal and is compatible with TTL logic levels. The cross-coupled gate nodes of the dynamic latch are conditionally discharged by circuitry which includes a ratio type first address inverter, and a second ratio type address inverter followed by a third ratioless inverter, whose output conditionally discharges one of the cross-coupled gate nodes of the dynamic latch. A separate write circuit drives each digit-sense column bus line, and includes a push-pull driver clocked by the third clock input signal. The pull-up and pull-down field effect transistors of the push-pull driver each have an exclusive OR type circuit for conditionally discharging the precharged gate electrodes of the pull-up and pull-down field effect transistors, depending on the voltages on the data input signal and the data control signal. The ratioless data control inverter and the data input inverter provide the complement signals required by the two exclusive OR type circuits.